STA and Timing Constraints

STA and Timing Constraints

Learn STA and Timing Constraints Concepts Deeply by vlsideepdive.

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Course Created by Industry Expert: Vikas Sachdeva

Vikas Sachdeva is a semiconductor design professional with more than 17 years of experience in the VLSI Industry. He was worked in the design, development, and deployment of multiple static and constraints products.

The webinar covers all basic concepts in Static Timing Analysis and Timing Constraints

• Introduction to Static Timing Analysis

• Timing Paths

• Startpoint, Endpoint, Combinational Logic

• Setup and Hold Check Definition

• Understanding details of setup slack calculation

• Multiple types of Timing Paths

• Design Rule Checks

• Timing checks on Async Pins

• Clock Gating Checks

• Timing Latches

• STA in presence of Multiple Clocks

• Timing Arcs

• Cell Delays and Models

• Impact of clock network on STA

• Understanding Text Report in STA

• Overview of SDC

• Clock and Generated Clock Definitions

• Clock Groups

• Clock Characteristics Specification

• Port Delays

• Timing Exceptions

• Other SDC commands

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Learn deeply

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Master essential concepts – Build confidence with hands-on learning. You will get to see concepts visually, interact with the key ideas and solve challenging problems that get you to really think and learn deeply.

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The course covers all basic concepts in Static Timing Analysis and Timing Constraints

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What you will learn

• Understand various STA checks for timing closure
• Understand Basics of Timing Constraints
• Ability to answer STA related interview questions

Rating: 0

Level: All Levels

Duration: 2.5 hours

Instructor: Vikas Sachdeva