VSD - Making the Raven chip: How to design a RISC-V SoC

VSD - Making the Raven chip: How to design a RISC-V SoC

Building a chip is like building a city...

This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.

If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

I welcome you to my webinar which was conducted on Mar 10, 2018. Enroll with myself, Tim Edwards and Mohamed Kassem, and rise above, by being a Core SoC designer and build your own datasheet.

This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design. Stay tuned and happy learning....

All the best, and I will see you in webinar..

Building a chip is like building a city....

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What you will learn

• Students will be able to build and configure their own SoC (System-On Chip)
• Students will be able to create their own defition of GPIO
• Understand decision making process, analog peripheral (ADC, DAC), digital peripheral (UART, flash controller), memory mapping, pad-frame, level-shifters, GPIO

Rating: 4.35

Level: Intermediate Level

Duration: 4.5 hours

Instructor: Kunal Ghosh